Silicon debug

SIDEBAR: The future of DFD methodologies For reasons of cost, performance, power, and miniaturization, many electronic systems that once consisted of several printed circuit boards are now manufactured as a single semiconductor device. As a result of this complexity, previously accessible system signals can no longer be observed, and the process of isolating and analyzing silicon problems has become tedious and time consuming. Using a process called silicon debug, engineers try to locate the sources of errors in their devices. They work to understand the root cause, correct or work around the root cause, and prepare the device so high-volume manufacturing can proceed. Engineers currently use various software and hardware tools to debug silicon. But because failure modes are complex and often arise only in corner-case scenarios under at-speed operation of the system, external debug equipment is insufficient to track down the source of system failures. Design-for-debug (DFD) methodologies offer a better solution. By embedding DFD logic right on a chip and then stimulating and evaluating it with commercial silicon debug and analysis tools, device manufacturers can make it possible for test engineers to view signals on a chip and track down the causes of failure. By adding DFD logic to chips, designers make it possible for test and product engineers to observe key internal signals and use a host-side commercial debugging tool to analyze and understand nonconformant chip behavior. One of the most popular silicon debug techniques is state dumping. This technique can be implemented using a standard on-chip DFD architecture that consists of only three debug features, which we call the " ABC " of silicon debug. An IEEE 1149.1 standard Test Access Port (TAP) controls all three features: